NONVOLATILE MEMORY MATRIX LOCATION Russian patent published in 2007 - IPC H01L27/115 

FIELD: electrically reprogrammable nonvolatile memory devices using micro- and nano-technology methods.

SUBSTANCE: proposed location has first-level semiconductor bus disposed on substrate that insulates it from other first-level buses; second-level metal bus crossing first-level bus; insulating layer, 3 to 100 nm thick, disposed under second-level bus; insulating slit in the form of insulating-layer open end in vicinity of crossing points of first-level buses and extreme ends of second-level buses; variable-conductivity material disposed in insulating slit whose conductivity changes when it passes electron flow; and medium above insulating slit surface affording particle exchange in variable-conductivity material. Disposed between insulator layer and first-level bus under insulating slit is n⁺ or n^- semiconductor layer^{of high current carrier concentration whose polarity of conductivity is reverse to that of first-level bus and its size in substrate plane is such that matrix first-level buses are reliably insulated from each other.}

EFFECT: improved rectifying properties of location, greatly reduced currents through semiconductor bus.

2 cl, 7 dwg