FIELD: electricity.
SUBSTANCE: in field MIS transistor drain and source regions each contain two serially connected sections, the main and the additional ones, at that the main sections of drain and source regions have high concentration of alloying admixture, and additional sections that are installed between channel and main sections have low concentration of alloying admixture. Abovementioned additional sections stretch into abovementioned semiconductor wafer deeper than the abovementioned main sections and enclose these main sections inside themselves, with their overlap in semiconductor wafer, and on the surface of semiconductor wafer border of this additional section on the one side is at least superposed with projection of one of gate sides on semiconductor wafer, and from the other sides it is distant from border of protective area at the value that is not less than sum of values of width of space charge areas formed in semiconductor wafer by drain, source regions and protective area, at that projection of end areas of gate ends onto surface of semiconductor wafer is superposed with border of protective area, and all surface of semiconductor wafer is coated with dielectric, the thickness of which does not exceed gate thickness.
EFFECT: increase of resistance to external actions, percentage of proper produce, fast-action.
5 dwg
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Authors
Dates
2008-11-27—Published
2006-12-07—Filed