MIS IC MANUFACTURING PROCESS Russian patent published in 2007 - IPC H01L21/8238 

FIELD: integrated microelectronics.

SUBSTANCE: proposed MIS IC manufacturing process includes organization of pocket regions on semiconductor silicon wafer, formation of gate insulator, field-effect gate electrodes, and mask, doping of gates, sources, and guard regions of one polarity of conductivity with low impurity concentration; formation of mask and doping of drain, source, and guard regions of other polarity of conductivity with low impurity concentration; deposition of silicon oxide layer and formation of separating zones between drain, source, and guard regions therein; formation of mask and doping of drain, source, and guard regions of one polarity of conductivity with high impurity concentration; formation of mask and doping of drain-source and guard regions of other polarity of conductivity with high impurity concentration; deposition of silicon oxide layer and its chemical and mechanical polishing until gate surface is opened; opening of contact windows in mentioned silicon oxide layer to provide access to diffusion regions; metal plating and formation of interconnections.

EFFECT: enhanced yield due to greater reproducibility of characteristics of passive and active integrated-circuit components; enhanced speed due to reduced throughput capacities of transistors in surface concentration of impurities in drain, source, and guard regions.

1 cl, 11 dwg