VERTICAL MIS TRANSISTOR OF INTEGRATED CIRCUIT Russian patent published in 1998 - IPC

FIELD: microelectronics, integrated circuits of large integration degree. SUBSTANCE: vertical MIS transistor of integrated circuit has semiconductor substrate of first type of conductance with semiconductor structure formed on it surrounded by insulating area and composed of upper and lower regions of second type of conductance which correspondingly are regions of source and drain and under-gate region of first type of conductance located between them. Structure has groove which bottom is situated in lower region of second type of conductance and which side surface carries insulated gate. Dimensions of groove in plan are smaller than dimensions of structure by double thickness of conductor to region of drain. Upper surface of structure is deeper relative to insulating area by value exceeding thickness of conductor in region of drain by 1.5 times. Conductor to region of source is located on surface of insulating area and is matched with region of drain with butt surface. Conductor to region of drain is arranged on dielectric-insulated surface of gate and is matched with region of drain on bottom of groove which walls are vertical. EFFECT: improved quality of MIS transistors. 2 dwg