FIELD: integral microelectronics, in particular, manufacturing of single-channel and complement MOS integral circuits for digital, linear and analog applications. SUBSTANCE: method involves sequential generation of contact points to semiconductor plate in layers of polycrystal silicon and under-gate oxide, application of second layer of polycrystal silicon and layer of silicon nitride, generation of gates, contact holes to semiconductor plate and isolation regions between drains and guarding regions in layers of silicon nitride and polycrystal silicon, doping regions of drains, sources and guarding regions, removal of silicon nitride from isolation regions between drains and guarding regions, thermal oxidizing, removal of silicon nitride in order to open contact holes to diffusion regions and gates, generation of metal wiring. EFFECT: increased good-to-bad output ratio, increased stability of integral circuits to adverse conditions, increased density, increased speed of integral circuits. 9 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| PROCESS OF MANUFACTURE OF MIS INTEGRATED CIRCUITS | 1995 |
|
RU2099817C1 |
| MIS IC MANUFACTURING PROCESS | 2006 |
|
RU2308119C1 |
| METHOD OF MANUFACTURING MUTUALLY ADDING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICES | 0 |
|
SU1023969A1 |
| FIELD MIS TRANSISTOR | 2006 |
|
RU2340040C2 |
| METHOD FOR MANUFACTURING SELF-SCALED BIPOLAR CMOS STRUCTURE | 2003 |
|
RU2234165C1 |
| METHOD FOR GENERATION OF CMOS-STRUCTURES WITH POLYSILICIC GATE | 1992 |
|
RU2056673C1 |
| PROCESS OF MANUFACTURE OF BICOS/BIMOS DEVICE | 1998 |
|
RU2141148C1 |
| PROCESS OF FABRICATION OF SELF-SCALING FIELD-EFFECT TRANSISTOR WITH STRUCT URE OF SUPERSELF-ALIGNED BIPOLAR TRANSISTOR | 2001 |
|
RU2230392C2 |
| SOLID STATE POWER TRANSISTOR PRODUCTION TECHNIQUE | 2016 |
|
RU2623845C1 |
| CMOS ARRAY CHIP MANUFACTURING PROCESS | 1996 |
|
RU2124252C1 |
