FIELD: integrated microelectronics, design and manufacture of single-channel and mutually complementary MIS integrated circuit for digital, linear and analog usage. SUBSTANCE: process of manufacture of MIS integrated circuits is based on sequential formation of gates and separating regions between drains and guarding zones in layers of silicon nitride and polycrystalline silicon, on removal of silicon nitride from separating regions between drains and guarding zones, on thermal oxidation , on removal of silicon nitride, on opening of contact windows to diffusion regions and on formation of interconnection with metal. EFFECT: increased output of good integrated circuits, their improved resistance to external effects thanks to planation of structure and high concentration of impurity in regions of guarding zones. 8 dwg
Title | Year | Author | Number |
---|---|---|---|
METHOD FOR MANUFACTURING OF MOS INTEGRAL CIRCUITS | 1995 |
|
RU2105382C1 |
MIS IC MANUFACTURING PROCESS | 2006 |
|
RU2308119C1 |
FIELD MIS TRANSISTOR | 2006 |
|
RU2340040C2 |
METHOD OF MANUFACTURING MUTUALLY ADDING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICES | 0 |
|
SU1023969A1 |
BIPOLAR CMOS DEVICE AND ITS MANUFACTURING PROCESS | 2003 |
|
RU2282268C2 |
METHOD FOR MANUFACTURING SELF-SCALED BIPOLAR CMOS STRUCTURE | 2003 |
|
RU2234165C1 |
METHOD FOR MANUFACTURING SILICON-ON-SAPPHIRE MIS TRANSISTOR | 2004 |
|
RU2298856C2 |
CMOS ARRAY CHIP MANUFACTURING PROCESS | 1996 |
|
RU2124252C1 |
PROCESS OF FABRICATION OF SELF-SCALING FIELD-EFFECT TRANSISTOR WITH STRUCT URE OF SUPERSELF-ALIGNED BIPOLAR TRANSISTOR | 2001 |
|
RU2230392C2 |
PROCESS OF MANUFACTURE OF CMOS STRUCTURE | 1990 |
|
RU1759185C |
Authors
Dates
1997-12-20—Published
1995-06-29—Filed