INPUT STRUCTURE FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-)(VERSIONS) Russian patent published in 2010 - IPC G06F7/50

Abstract RU 2378682 C2

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out arithmetic operations of summation and subtraction in position-sign codes. Each bit of the adder is made in form of structure-equivalent channels - positive and conditionally negative. In one version of implementation, the i^th bit of each channel contains two OR logic components, two NAND logic components, two inverter gates and an AND logic component.

EFFECT: simplification of functional structure of the adder and faster operation.

2 cl, 13 dwg

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RU 2 378 682 C2

Authors

Petrenko Lev Petrovich

Dates

2010-01-10—Published

2007-12-17—Filed