FUNCTIONAL DESIGN FOR UPDATING ARGUMENTS OF INTERMEDIATE SUM ±[S''i] OF PARALLEL ADDER IN POSITION-SIGN CODES f(+/-) Russian patent published in 2009 - IPC G06F7/50

Abstract RU 2362204 C9

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out summation and subtraction operations in position-sign codes. Each bit of the adder is made in form of two design-equivalent channels - for positive and conditionally negative. In one version of the invention, the i^th bit of each channel contains six NOR elements.

EFFECT: simple functional design of the adder.

9 cl, 41 dwg

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RU 2 362 204 C9

Authors

Petrenko Lev Petrovich

Dates

2009-07-20—Published

2007-12-17—Filed