FIELD: information technologies.
SUBSTANCE: device comprises two CMDS inverters, two recording transistors of n-type, two transistors for reading of n-type and reading transistor of p-type. Output of the first CMDS inverter is connected to input of the second CMDS inverter, to gate of the first reading transistor of n-type and via the first recording transistor is connected to direct data bus. Output of the second CMDS inverter is connected to input of the first CMDS inverter, to gate of reading transistor of n-type and via the second recording transistor of n-type is connected to complementary data bus. Gates of recording transistors of n-type are connected to address recording bus. The first and second reading transistors of n-type are connected serially between shift bus and reading bus. Reading transistor of p-type is connected parallel to the first reading transistor of n-type, and gate of the second reading transistor of n-type is connected to address reading bus.
EFFECT: improved efficiency of device.
1 dwg
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Authors
Dates
2010-06-10—Published
2008-12-12—Filed