MEMORY CELL FOR HIGH-SPEED EEPROM WITH CONTROLLED POTENTIAL OF UNDER-GATE REGION Russian patent published in 2012 - IPC G11C11/40 G11C16/04 

FIELD: information technology.

SUBSTANCE: memory cell for high-speed controlled gate-region potential EEPROM, the electric circuit of the memory cell having an n(p)-MOS transistor, first and second diodes, a capacitor, a number, an address and a bit line, wherein the cathode (anode) of the first diode is connected to the number line and the source of the n(p)-MOS transistor, its anode is connected to the anode of the second diode, the region under the gate of the n(p)-MOS transistor and the first lead of the capacitor, the second lead of which is connected to the gate of the n(p)-MOS transistor and the address line, and the cathode of the second diode is connected to the drain region of the n(p)-MOS transistor and the bit line, wherein the electric circuit of the memory cell additionally includes a p(n)-field-effect transistor, a common and control line, wherein its source is connected to the region under the gate of a MOS transistor, the gate is connected to the control line and the drain is connected to the common line.

EFFECT: higher reliability of memory cell work.

2 cl, 6 dwg