METHOD OF MAKING SELF-SCALED SELF-ALIGNED TRANSISTOR STRUCTURE Russian patent published in 2011 - IPC H01L21/331 

FIELD: physics.

SUBSTANCE: method of making self-scaled self-aligned transistor structure involves formation of a first dielectric layer on a substrate having first type conductivity, continuous introduction of impurities having second type conductivity with subsequent annealing to form a collector region, formation of a first polycrystalline silicon layer on the first dielectric layer, formation of a second dielectric layer thereon, opening windows to form a slit under the insulating region and a contact to the substrate, etching in the window a second dielectric layer, a first polycrystalline silicon layer, a first dielectric layer and partially substrates at a depth equal to the space-charge region, formation a third dielectric layer on the lateral walls of the slit, formation of an anti-channel region at the bottom of the slit, formation of a fourth dielectric layer in the slit, local removal of the third and fourth dielectric layers from the bottom of the slit under the contact to the substrate, filling the slit with a second layer of polycrystalline silicon, planarisation of the latter to the second dielectric layer, etching the second polycrystalline silicon layer in the slit by a depth equal to the second dielectric layer, local doping of the contact to the substrate with an impurity having first type conductivity, formation of a fifth dielectric layer over the second polycrystalline silicon layer in the slit, opening windows in the second dielectric layer on the site of the future contact up to the collector region and on the site of future emitter and base regions, between which lies the future contact to the base region, etching the first polycrystalline silicon layer by half its thickness, local etching of the first polycrystalline silicon layer on the site of the future contact to the collector region to the first dielectric layer, formation of a sixth dielectric layer on the vertical walls of the etched windows, etching the second dielectric layer, etching the first polycrystalline silicon layer on the site of the future emitter and the contact to the base region up to the first dielectric layer, etching the first dielectric layer from the bottom of the windows, formation of a hydride epitaxial poly-monocrystalline layer, where monocrystalline silicon is grown in the opened windows up to the silicon, and polycrystalline silicon is grown over the dielectric and polycrytalline layers, planarisation of the polycrystalline layer to the fifth dielectric layer, local doping of the contact to the collector region with an impurity having second type conductivity, local doping of the contact to the base region with an impurity having first type conductivity, thermal annealing, local doping of the base region and under-doping of its contact with an impurity having first type conductivity, local doping of the emitter region and under-doping of the contact to the collector region with an impurity having second type conductivity, thermal annealing to form regions of a transistor structure, formation of the layout of the transistor structure with a refractory silicide.

EFFECT: high density of assembling transistor structures and improved parametres of transistors based on said structures.

2 cl, 15 dwg, 1 ex