METHOD AND APPARATUS FOR ENABLING COOPERATIVE SIGNALLING OF SHARED BUS INTERRUPT IN MULTI-RANK MEMORY SUBSYSTEM Russian patent published in 2011 - IPC G06F13/16 

FIELD: information technology.

SUBSTANCE: memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.

EFFECT: possibility of signalling a shared bus interrupt in a multi-rank memory subsystem.

24 cl, 7 dwg