FIELD: radio engineering, communication.
SUBSTANCE: high-speed N-bit combined analogue-to-digital converter (ADC) includes an input parallel M-bit ADC1, an M-bit digital-to-analogue converter (DAC1), using a common serial resistance divider, a reference voltage Vref source, a sampling and storage device (SSD) for the difference signal of the input of the ADC and output voltage of the DAC and a pipelined (M-M+1)-bit ADC2. Calibration includes calculating and loading into DAC2 a calibration code CR and calibration codes CSi of each segment, used during normal operation as additive adjustments to the output code of the ADC, wherein a signal close to zero is generated through a unit transmission coefficient of the first stage of an ADC2 pipeline. In ADC, using SSD and ADC2 with double sampling, the DAC2 and Vref2 source are doubled and generate voltages Vref2A and Vref2B separately for each of two samplers A and B.
EFFECT: high accuracy of calibrating an N-bit combined ADC by reducing the conversion error of the ADC by reducing the effect of mismatch of parameters of components via calibration.
8 cl, 6 dwg, 1 tbl
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Authors
Dates
2014-06-27—Published
2013-01-15—Filed