METHOD OF DETERMINING THERMAL IMPEDANCE OF VERY LARGE SCALE INTEGRATED CIRCUITS - MICROPROCESSORS AND MICROCONTROLLERS Russian patent published in 2014 - IPC G01R31/28 

FIELD: physics; control.

SUBSTANCE: method is meant for use during outgoing and incoming quality control of very large scale integrated (VLSI) circuits - microprocessors and microcontrollers and evaluating temperature margins thereof. A special "warm up" test and a control program are loaded into the inspected VLSI circuit which is mounted on a heatsink and is connected to a power supply. A periodic heating mode is turned on by switching the inspected VLSI circuit from a mode of executing the special test to a standby mode with frequency Ω and duty ratio 2. The method includes, at modulation frequency Ω, selecting and measuring the amplitude $$I_{m1}^{\text{cons}}\left(\Omega \right)$$ of the first harmonic of current consumed by the inspected VLSI circuit, the amplitude $$U_{m1}^{TP}\left(\Omega \right)$$ of the first harmonic of a temperature-sensitive parameter with a known negative temperature coefficient K_T, e.g. voltage across a p-n junction built into the kernel of the VLSI circuit or high-level voltage across one of the leads of the VLSI circuit loaded with a resistive load, the logic state of which does not change when the VLSI circuit is switched from one mode to the other, and the phase shift φ(Ω) between the first harmonic of current consumed by the inspected VLSI circuit and the first harmonic of the temperature-sensitive parameter. The magnitude of thermal impedance of the inspected VLSI circuit at frequency Ω is determined using the formula: $$\left|Z_T\left(\Omega \right)\right|=\frac{U_{m1}^{TP}\left(\Omega \right)}{K_T{U}_{\sup }{I}_{m1}^{\text{cons}}\left(\Omega \right)},$$ where U_sup is supply voltage of the inspected LSI circuit, and the phase φT(Ω) of thermal impedance of the inspected VLSI is defined as the phase difference between the first harmonic of the temperature-sensitive parameter and the first harmonic of current consumed by the inspected VLSI circuit minus 180°.

EFFECT: high efficiency of the method.

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