FIELD: electrical engineering.
SUBSTANCE: embodiments of the present invention are directed to creating packaged integrated circuit (IC) comprising a first integrated circuit chip that is at least partially integrated in the first seal layer, and second IC chip, at least partially embedded in the second sealing layer. First crystal may comprise a first plurality of interconnect structures at the crystal level located on the first side of the first sealing layer. This packaged IC may also contain a plurality of electric route elements, at least partially embedded in the first sealing layer and configured to route electrical signals between the first side and the second side of the first sealing layer. Second side of the layer can be opposite to the first side of said layer. Second crystal may have a second group of several compound structures at the crystal level, which can be electrically connected to at least a subset of a plurality of a plurality of electric route elements by means of wire bridges. Second sealing layer is in direct contact with the first sealing layer, said first sealing layer covering the second side of said second crystal.
EFFECT: invention makes it possible to reduce the length of the connections between the crystals in a packaged multicrystal circuit while maintaining a small form factor.
17 cl, 8 dwg
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Authors
Dates
2018-08-08—Published
2014-09-26—Filed