FIELD: physics.
SUBSTANCE: invention relates to methods of element-by-element duplication in nano-and micro-digital transistor chips exposed to radiation. In the proposed method for each transistor logic element set identical duplicate logic element, logic elements that do not have memory are used as duplicating elements; logic elements that overlap each other are located at a distance between them greater than the size of the damaged area of the chip from one radiation particle. Each transistor included in the duplicating logic elements is executed in the form of a quadrated transistor, which represents a four of single transistors connected in parallel and in series.
EFFECT: significant increase in the fault tolerance of chips compared to the duplication method without using fourfold redundancy of single transistors.
3 cl, 3 dwg
