FIELD: computer technology.
SUBSTANCE: invention relates to the field of digital computing and is intended for modeling combinatorial problems in the design of computer systems. The expected result is achieved due to the fact that in a device containing the first shift register, the second shift register, a block for forming permutations, a permanent memory block, a block for storing the best option, a switch, an ALU, an arc selection decoder, a reversible cell counter, a RAM block, the first comparison element, a count start trigger, a mode trigger, an arc counter, an arc lock decoder, an arc number register, a minimum weight register, an electronic graph model, a group of elements OR, a group of elements AND, first and second elements AND, the second block of elements OR, the third element AND, the first delay element, the second delay element, the first block of elements OR, a lower evaluation block is introduced containing a group of memory modules of a hybrid multiprocessor system, a group of processors of a hybrid multiprocessor system, a group of intermediate adders and a common adder.
EFFECT: minimizing the intensity of interaction between processes and data.
1 cl, 3 dwg
