FIELD: pulse computing.
SUBSTANCE: circuit containing two AND-OR-NOT elements, two OR-NOT elements, three OR-NOT elements, a disparity element with two paraphase inputs and one paraphase output, two AND-NOT elements, two hysteresis triggers, an inverter, positive, negative and zero components of the first ternary summand, positive, negative and zero components of the second ternary summand, two paraphase transfer inputs, two paraphase transfer outputs, positive, negative and zero components of the ternary sum and indicator output, introduced two more AND-OR-NOT elements, two OR elements, three AND-NOT elements, one OR-AND element.
EFFECT: implementation of a single-digit ternary adder circuit with a single addend spacer without increasing hardware costs and without reducing performance.
1 cl, 2 tbl, 1 dwg
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