SELF-TIMED SINGLE-BIT TERNARY ADDER WITH ZERO SPACER AND INCREASED FAULT TOLERANCE Russian patent published in 2023 - IPC H03K3/00 

FIELD: pulse and computer technology.

SUBSTANCE: in a circuit comprising two OR-AND-NOR elements, two OR-AND-NOT elements, two AND-OR-NOT elements, three NOR-NOT elements, two AND elements, one AND-OR element, one disparity element with paraphase inputs and output, two hysteresis triggers, positive, zero and negative components of two ternary terms, direct and inverse components of the first paraphase transfer input, direct and inverse components of the second paraphase transfer input, direct and inverse components of the first paraphase transfer output, direct and inverse components of the second paraphase transfer output, positive, zero and negative components of the ternary sum, indicator output, five elements of equivalence, a second AND-OR element and additional connections between the elements of the circuit are introduced.

EFFECT: increased fault tolerance of a self-timed single-bit ternary adder by masking the incorrect state of the adder elements resulting from a short-term single logical failure.

1 cl, 4 dwg, 3 tbl