FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering. Device comprises external inputs of ID data and output of number of cycles by IUL states, groups of external outputs of cycle parameters QB, number of QC cycles and number of cycles by QS states, first RS trigger of start-stop TSS 1, second delay trigger TZ 2, first AND element with inverse input 3, second element AND 4, first 5 and second 6 OR elements, first reversible bit counter CTB 7, NOR element 8, flags register RF 9, third trigger of the first bit of cycle TRB 10, second counter of number of cycles CTC 11, third counter of interval CTI 12, output buffer of OB 13, first 14 and second 15 decoders DC, first 161, …, 16K and second 171, …, 17K groups of counters (where K is the number of positive and negative deviations (states) of cumulative sums), first 181, …, 18K and second 191, …, 19K groups of decoders DC, first 20[0:M, 1:K] and second 21[0:M, 1:K] matrix of counters, each containing (M+1) rows and K columns (where M is the maximum number of identical states in the cycle) and element OR 22, as well as external inputs of clock signal 1C, device start START and stop device STOP, internal flags F0 of the zero state of the bit counter CTB 7, FE1 of the end of the cycle, FE2 of the end of the sequence, FW1 of the cycle recording and FW2 of the deviation recording, external exchange control bus EO, external flags FF "Buffer is full", FZ "Buffer is empty", FEQ "equality of zero and one bits", FG1 "ones are more than zeros", QFM state exceeding and QFW exceeding number of cycles.
EFFECT: possibility of calculating cumulative sums, detecting and counting cycles of deviation of sums from zero, as well as counting the number of deviations by states and the number of cycles by states, and determining the ratio between the number of unit and zero bits in the input binary sequence.
1 cl, 4 dwg
