PROCESS PLANATION OF INTEGRATED CIRCUITS Russian patent published in 1994 - IPC

Abstract RU 2024992 C1

FIELD: microelectronics. SUBSTANCE: process involves plasma etching of integrated circuits in individual diode reactor under pressure of 150 to 600 Pa and density of HF power from 3.5 to 8.0 W/sq.cm in four-component mixture with following proportion of components, percent by volume; octofluoridepropane or hexafluoridethane 13-70; sulfur hexafluoride or trifluoride 7-25; oxygen 5-10; inert gas 18-52. EFFECT: increased uniformity and rate of planation, improved selectivity of etching, reduced precipitation of fluoridecarbon polymers on surfaces subjected to planation. 3 dwg

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RU 2 024 992 C1

Authors

Bliznetsov V.N.

Gushchin O.P.

Zheleznov F.K.

Trusov A.A.

Jachmenev V.V.

Dates

1994-12-15—Published

1992-06-11—Filed