METHOD FOR GENERATION OF CMOS-STRUCTURES WITH POLYSILICIC GATE Russian patent published in 1996 - IPC

FIELD: microelectronics, methods for manufacturing of semiconductor integral CMOS-circuits. SUBSTANCE: method involves etching oxide layer on areas of drains and sources of n-channel transistors, doping polysilicon, generating mask, which corresponds to topological pattern of gate electrode, oxidizing polysilicon in areas which are not protected by mask. Simultaneously with generation of control gate electrode, areas of drains and sources of n-channel transistors are doped from layer of doped polysilicon. Drains and sources of p-channel transistors are manufactured by introduction of p-type dope when oxide layer over areas of drains and sources of p-channel transistors is removed. EFFECT: increased functional capabilities. 2 cl, 1 dwg