PROCESS OF MANUFACTURE OF BICOS/BIMOS DEVICE Russian patent published in 1999 - IPC

FIELD: microelectronics. SUBSTANCE: invention is related to technology of manufacture of BICOS/BIMOS devices in which complementary bipolar and field-effect transistors are formed on one crystal. According to invention first layer of polysilicon and oxide under gate are left in pockets of field-effect transistors with overlapping of oxide by polysilicon layer by value equal to lithography error, in pocket of first bipolar transistor in point of location of window for emitter with overlapping by polysilicon by value equal to lithography error and in pocket of second bipolar transistor with exception of point of location of emitter. In addition during doping of second polysilicon layer point of location of base electrode of first bipolar transistor is doped. First high-temperature firing is conducted before formation of electrodes from third polysilicon layer and third polysilicon layer is doped first with impurity of second type of conductance above regions of drains and sources of n channel field and collector electrodes of second bipolar transistors. Then third polysilicon layer is doped with impurity of first type of conductance above regions of drains and sources of p channel field-effect transistor, emitter and collector electrodes of first bipolar and base electrode of second bipolar transistors. Then second firing is conducted at temperature below that of first firing. Later electrodes to regions of drains and sources of field- effect transistor, to regions of emitter and collector of first bipolar and to regions of passive base and collector of second bipolar transistor are formed from third polysilicon layer, then second silicide and second insulating layers are precipitated. EFFECT: increased degree of integration, speed of response and percentage of good BICOS/BIMOS devices thanks to improvement of process of formation of electrodes to drains and sources of field-effect transistors and electrode of emitter from third polysilicon layer that diminish capacitances of junctions and resistance value of base and to exclusion of action of plasma on silicon surface in active regions of transistors. 10 dwg