PROCESS OF FABRICATION OF SELF-SCALING FIELD-EFFECT TRANSISTOR WITH STRUCT URE OF SUPERSELF-ALIGNED BIPOLAR TRANSISTOR Russian patent published in 2004 - IPC

FIELD: microelectronics, technology of manufacture of field-effect transistors with MOS structure. SUBSTANCE: process of fabrication of transistor includes formation of first dielectric, pickling of windows in first dielectric by vertical pickling separately for regions of drain and source with overlapping by windows of beak of first dielectric towards dielectric made by local oxidation and pickling depth ensuring planarity of dielectric in windows from surface of silicon and distance between windows for regions of drain and source exceeding width of gate of field-effect transistor, pickling of horizontal and inclined sections of second dielectric above regions of beak up to first layer of polycrystalline silicon. After stripping of first layer of polycrystalline silicon with solvent second layer of polycrystalline silicon is deposited, it is doped to form poorly doped regions of drain and source of field-effect transistor, horizontal and inclined sections of second layer of polycrystalline silicon are pickled above regions of beak to depth of silicon and first dielectric, surface of silicon and second layer of polycrystalline silicon are oxidized to depth not less than thickness of dielectric located under gate, third layer of polycrystalline silicon is deposited, gate is formed, heavily doped regions of drain and source are formed by diffusion from first layer of polycrystalline silicon and poorly doped regions of drain and source are formed by diffusion from second polycrystalline layer. EFFECT: complete simultaneous self-alignment of all basic elements of field-effect transistor with provision for self-scaling of length of gate to values substantially less than value of minimal size in lithograph. 4 cl, 8 dwg