METHOD FOR MANUFACTURING SELF-SCALED BIPOLAR CMOS STRUCTURE Russian patent published in 2004 - IPC

FIELD: microelectronics; manufacture of bipolar complementary metal-oxide-semiconductor structures.

SUBSTANCE: proposed method for manufacturing bipolar CMOS structures including bipolar and field-effect transistors having components of submicron dimensions smaller than design standards for lithography includes following operations: pockets of first and second polarities of conductivity and first insulating layer are made in silicon substrate, thin silicon oxide is formed, polycrystalline silicon electrode layer is deposited and doped at locating point of bipolar transistor with impurity of first polarity of conductivity to produce high-doped regions of passive base in silicon and with impurities of first and second polarities of conductivity, respectively, at location points of field-effect transistors with same polarity of channel conductivity to produce high-doped regions of drain and source, and electrodes with vertical walls are formed from this layer. Deposition of first polycrystalline silicon layer is followed by its doping first with impurity of first polarity of conductivity to produce low-doped regions at location points of bipolar transistor and low-doped regions of drain and source of field-effect transistor with channel polarity of conductivity same as that of given impurity; then it is doped with impurity of second polarity of conductivity to produce low-doped regions of drain and source of second field-effect transistor with channel polarity same as that of second impurity; first layer of polycrystalline silicon is etched after second insulating layer until thin silicon oxide layer is obtained, the latter is removed to expose silicon at the same time partially etching it under polycrystalline silicon layer; silicon is doped with impurity of first polarity of conductivity only in bipolar transistor region, and wall insulator is formed. Gate insulator is formed on silicon, then it is removed in bipolar transistor boxes, and second layer of polycrystalline silicon is doped upon deposition with impurity of second polarity of conductivity at location point of bipolar transistor emitter and that of gate of field-effect transistor with channel polarity of conductivity same as that of given impurity; then polycrystalline silicon is doped with impurity of first polarity of conductivity at location point of gate of field-effect transistor with channel polarity of conductivity same as that of given impurity.

EFFECT: improved electrical characteristics of transistors.

6 cl, 2 dwg