METHOD FOR MANUFACTURING SELF-ALIGNING PLANAR TWO-GATE MOS TRANSISTOR ON SILICON-0N-INSULATOR SUBSTRATE Russian patent published in 2007 - IPC H01L21/336 

FIELD: integrated-circuit manufacture on silicon-on-insulator substrate; transistor structures of extremely minimized size for ultra-high-speed integrated circuits.

SUBSTANCE: proposed method for manufacturing self-aligning planar two-gate MOS transistor on SOI substrate includes production of work and insulator regions of two-gate transistor on wafer surface, modification of hidden oxide, formation of tunnel in hidden oxide, formation of polysilicon gate and drain-source regions; upon formation of insulator and work regions; supporting mask layer is deposited onto substrate surface and ports are opened to gate regions to conduct ionic doping of hidden oxide with fluorine through them; then doped part of oxide under silicon is removed by selective etching to form tunnel in hidden oxide whereupon silicon surface is oxidized in open regions above tunnel and gate is formed; port in supporting layer and tunnel are filled with conductive material, and gate-source regions are produced upon etching supporting layer using gate as mask. Transistor structure channel length is up to 10 nm.

EFFECT: reduced length of transistor structure channel.

2 cl, 1 dwg