FIELD: microelectronics; manufacture of large-scale bipolar integrated circuits using self-aligned technology. SUBSTANCE: process includes production of buried layers of first type of conductivity and deposition of epitaxial layer of second type of conductivity, formation of first dielectric on surface and etching of cuts for base in it, deposition of first polysilicon film, doping of polysilicon with impurity of first type of conductivity, deposition of second dielectric film whose thickness is of at least two alignment errors on lithography, formation of photoresist mask so that boundaries of emitter cuts in photoresist are above vertical sections of second dielectric film formed on base cut steps and arranged closer to one alignment error on lithography from every side wall of vertical dielectric sections, etching of dielectric on horizontal sections up to polysilicon, etching of polysilicon, doping of silicon with impurity of first type of conductivity, formation of near-wall dielectric, deposition of second polysilicon film, formation of emitter and base regions, production of contacts for them, and metal evaporation. EFFECT: reduced size of emitter without impairing other characteristics of transistor and without using complex processes liable to reduce yield. 11 dwg
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Authors
Dates
1998-05-10—Published
1995-11-09—Filed