FIELD: electronics, manufacture of bipolar transistors with regions of base and emitter ' close to wall ' of regions of base and emitter. SUBSTANCE: process of manufacture of bipolar transistor includes formation of local latent layer in silicon substrate, deposition of epitaxial layer, doping of points of future arrangement of regions of emitter and base ' close to wall ' of dielectric with base dopant, formation of insulating layer of dielectric, formation of base limited by region of dielectric, formation of layer of polycrystalline silicon doped with emitter dopant, formation of polycrystalline electrode, formation of emitter manufactured by diffusion from polycrystalline electrode and limited by region of dielectric at least on one side. EFFECT: prevention of electric punch-through of base in region ' close to wall ' of dielectric beneath emitter due to narrowing of width of base. 8 dwg
Title | Year | Author | Number |
---|---|---|---|
PROCESS OF MANUFACTURE OF BIPOLAR COS/MOS STRUCTURE | 1998 |
|
RU2141149C1 |
BICMOS DEVICE AND PROCESS OF ITS MANUFACTURE | 1996 |
|
RU2106719C1 |
BIPOLAR CMOS STRUCTURE MANUFACTURING PROCESS | 1995 |
|
RU2106039C1 |
BIPOLAR TRANSISTOR MANUFACTURING PROCESS | 1995 |
|
RU2110868C1 |
PROCESS OF MANUFACTURE OF BICOS/BIMOS DEVICE | 1998 |
|
RU2141148C1 |
METHOD FOR MANUFACTURING SELF-SCALED BIPOLAR CMOS STRUCTURE | 2003 |
|
RU2234165C1 |
BIPOLAR CMOS DEVICE AND ITS MANUFACTURING PROCESS | 2003 |
|
RU2282268C2 |
PROCESS OF FABRICATION OF SELF-SCALING FIELD-EFFECT TRANSISTOR WITH STRUCT URE OF SUPERSELF-ALIGNED BIPOLAR TRANSISTOR | 2001 |
|
RU2230392C2 |
STRUCTURE OF BIPOLAR TRANSISTOR WITH EMITTER OF SUB-MICRON DIMENSIONS, AND METHOD FOR MANUFACTURING SAID STRUCTURE | 2003 |
|
RU2279733C2 |
METHOD FOR MANUFACTURING COMPLEMENTARY VERTICAL BIPOLAR TRANSISTORS AS PARTS OF INTEGRATED CIRCUITS | 2003 |
|
RU2244985C1 |
Authors
Dates
1997-12-20—Published
1995-06-29—Filed