FIELD: integrated circuits using bipolar vertical p-n-p transistors. SUBSTANCE: method involves rendering near-surface layer amorphous and introducing p-type dope at point of future location of buried p+-type layers in single implanting process using dope BF2, recrystallizing and baking of amorphous layer, settling down epitaxial layer forming side insulation, producing surface dielectric, forming collector and base regions of transistor, forming base region of transistor, forming emitter. EFFECT: facilitated procedure. 2 cl, 7 dwg
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