METHOD FOR PRODUCING SILICON-ON-INSULATOR STRUCTURES FOR VERY LARGE-SCALE INTEGRATED CIRCUITS (OPTIONS) Russian patent published in 2000 - IPC

FIELD: microelectronics. SUBSTANCE: method involves formation of insulating layer, deposition of polycrystalline insulating layer and metal layer on first silicon plate, its connection to second silicon plate so that deposited layers occur between plates, splicing of joined plates by heating them to form metal silicide layer between them, thinning of one of silicon plates, formation of depression in this plate around silicon regions designed to mount very large-scale IC components, covering of depression walls with insulation, formation of field-effect transistors in insulated regions of silicon, thinning of second silicon plate which is in immediate contact with metal silicide layer, formation of depression in this silicon plate and in metal silicide layer down to insulation layer, and formation of bipolar transistors in insulated regions of silicon above metal silicide layer. EFFECT: provision for manufacturing structure with field-effect and bipolar transistors. 11 cl, 22 dwg