METHOD FOR PRODUCING SILICON-ON-INSULATOR STRUCTURE FOR VERY LARGE-SCALE INTEGRATED CIRCUITS Russian patent published in 2004 - IPC

FIELD: microelectronics; production of silicon-on-insulator structures for very large-scale integrated circuits.

SUBSTANCE: proposed method includes deposition of first metal layer on first silicon wafer carrying insulating layer, its connection to second silicon wafer so that deposited layers occur between wafers, splicing of connected wafers by heating until metallide-silicide metal layer is formed between them, and thinning of one of silicon wafers; deposited on first-wafer first metal layer is layer of low-melting metal or alloy and on second layer, layers of metal and low-melting metal or alloy similar to layers deposited on first wafer; splicing is conducted in minimum two stages: first is low-temperature stage with temperature slightly higher than melting point of low-melting metal or alloy but lower than diffusion process promotion temperature, in which case liquid metal phase is formed; during second stage temperature is maintained at value providing for producing solid metallide phase; then one of wafers is thinned.

EFFECT: enhanced quality of structures and their yield due to producing continuous boundary between wafers without cavities.

8 cl, 4 dwg