SILICON-ON-INSULATOR STRUCTURE FOR VERY LARGE-SCALE INTEGRATED CIRCUITS (DESIGN VERSIONS) Russian patent published in 2000 - IPC

FIELD: microelectronics. SUBSTANCE: structure incorporating first and second silicon layers, insulating layer, metal silicide layer in-between, regions isolated by second insulating layer in silicon layer designed for carrying components of very large-scale integrated circuit, and field-effect transistors in isolated silicon regions has its silicide metal layer and its isolated silicon regions above silicide metal layer carrying both field-effect and bipolar transistors, mentioned metal silicide layer being used as latent low-resistance layer contacting substrate of field-effect transistors and collector region of bipolar transistors. Mentioned bipolar transistors have emitter, base, and collector regions with respective contacts and metal silicide layer used as latent low-resistance layer in collector region as well as local highly doped regions whose collector polarity of conductivity between base and silicide metal layer and between contacts to collector region and silicide layer ensures resistive contact to metal silicide layer. EFFECT: improved design of silicon-on-insulator structure. 7 cl, 4 dwg