FIELD: electronic engineering. SUBSTANCE: module 4 has first and second semiconductor integrated circuits 40, 6 and insulating strip layer 5. First semiconductor integrating circuit 40 has wiring surface that carries first contact pads. Insulating strip layer 5 has first and second opposing adhesive surfaces 51. First adhesive surface is adhered to contact-pad surface on first integrated surface 40. Insulating strip layer 5 is provided with holes at locating points of first contact pads which are meant to open the latter. Each hole is bounded by wall; the latter and respective contact pad form cavity to receive the contact. Electricity-conducting contacts 54 are inserted in respective cavities. Second semiconductor integrated circuit 6 has its wiring surface 61 joined with second adhesive surface 51 of insulating strip layer 5. Wiring surface 61 carries contact pads 60 connected to electricity-conducting contacts 54 to provide for electrical connection to first contact pads. Proposed process for manufacturing module 4 given in description of invention provides for locating great number of memory integrated circuits without increasing size of printed-circuit board. EFFECT: provision for reducing length of signal transmission channel to minimize delay time. 21 cl, 11 dwg
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Authors
Dates
2001-06-27—Published
1999-07-13—Filed