DYNAMIC MEMORY LOCATION Russian patent published in 2003 - IPC

FIELD: nanoelectronics. SUBSTANCE: novelty is introduction of bipolar transistor and nonlinear resistor in circuit of dynamic random-access memory location which makes it possible to amplify data signal thereby enabling fast recharge of parasitic capacitor C_p of discharge bus Y. Memory location is functionally integrated component wherein collector zone of bipolar transistor functions at the same time as gate subzone of MOS field-effect transistor; drain zone of the latter forms base zone of bipolar transistor, and resistor is formed by quasi-neutral part of active base zone of p^- bipolar transistor. Functional integration into single system of MOS field-effect transistor, bipolar transistor, and resistor results in implementing memory location whose layout dimensions and manufacturing process are similar to those of single-transistor dynamic random- access memory location. EFFECT: enhanced operating reliability and speed of memory location. 2 cl, 4 dwg