STRUCTURE OF BIPOLAR TRANSISTOR WITH EMITTER OF SUB-MICRON DIMENSIONS, AND METHOD FOR MANUFACTURING SAID STRUCTURE Russian patent published in 2006 - IPC H01L29/73 H01L21/331 

Abstract RU 2279733 C2

FIELD: micro-electronics.

SUBSTANCE: structure of bipolar transistor with emitter of sub-micron dimensions contains silicon substrate of first conductivity type with concealed layer of second conductivity type, epitaxial layer of second conductivity type, positioned on the substrate, side insulation in epitaxial layer around collector area of transistor of second conductivity type above the concealed layer, first layer of dielectric in epitaxial layer with windows, electrode of emitter made of first layer of polycrystalline silicon, covered by second layer of dielectric and positioned in area of base, area of emitter of second conductivity type in silicon below emitter electrode from first layer of polycrystalline silicon, wall dielectric, insulating ends of emitter electrode from first layer of polycrystalline silicon, covered by second layer of dielectric, areas of passive base of first conductivity type, electrode from second layer of polycrystalline silicon, positioned above area of base and emitter electrode and having an opening above emitter electrode, enough for positioning a contact window to emitter electrode in special dielectric and metallic electrode in contact window, layer of special dielectric on the surface of structure, contact windows, metallic electrodes. Concealed layer is positioned in the area of additional second concealed layer with concentration of admixture of second conductivity type, slightly exceeding concentration of admixture in substrate, in windows of first dielectric on silicon below electrode of emitter of polycrystalline silicon, thin layer of silicon oxide is positioned, having partial opening below electrode of emitter for calculated value and filled with additional third layer of polycrystalline silicon, which on the ends of emitter electrode has an oxidized portion in form of silicon oxide as wall dielectric. Also disclosed is the method for manufacturing aforementioned structure.

EFFECT: increased speed of operation of transistor.

2 cl, 12 dwg

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RU 2 279 733 C2

Authors

Dolgov Aleksej Nikolaevich

Eremenko Aleksandr Nikolaevich

Klychnikov Mikhail Ivanovich

Kravchenko Dmitrij Grigor'Evich

Lukasevich Mikhail Ivanovich

Manzha Nikolaj Mikhajlovich

Dates

2006-07-10Published

2003-05-22Filed