CMOS/SOI MRAM MEMORY INTEGRATED WITH VLSI AND METHOD FOR PRODUCTION THEREOF (VERSIONS) Russian patent published in 2014 - IPC H01L21/8229 

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering, particularly MRAM cell array circuits which employ spin-transfer torque magnetoresistive random-access memory technology. A method of making CMOS/SOI MRAM integrated into a basic processing route in order to form an initial planar VLSI heterostructure of CMOS/SOI technology with STI insulation, used as a substrate, and subsequently forming thereon an MRAM array, includes successively forming in Si device layer of a SOI heterostructure regions of n- and p-pockets, STI insulation, n⁺- and p⁺-polysilicon gates for n- and p-channel transistors, respectively, regions of high-ohmic drains and sources of MOS transistors, p⁺-drains which run to the bottom of the device layer, as well as layers of self-aligned titanium silicide and a multilayer metal coating, then on the formed VLSI structure, after the third metal coating layer, forming an MRAM array, which includes a freely re-magnetising ferromagnetic layer (SS), a fixed magnetisation ferromagnetic layer (FS) and a tunnel insulation layer (IS) between the SS and the FS, and then forming a fourth level of metal coating and a protective dielectric layer.

EFFECT: integrating the technology of forming an MRAM array with improved magnetic hysteresis of magnetic elements into a CMOS/SOI VLSI structure.

36 cl, 56 dwg