METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH GATE ELECTRODE OF NANOMETRIC LENGTH Russian patent published in 2004 - IPC

FIELD: nanoelectronics; manufacture of semiconductor devices, integrated circuits, and functional microelectronic devices.

SUBSTANCE: proposed method designed for manufacturing semiconductor device with gate electrode whose length is reduced to a few tens of nanometers and for production of nanometric transistor components (drain, gate, source) using self-aligned technology and any lithography in manufacturing semiconductor devices includes separation of device active area on substrate; formation of gate insulator incorporating first and second insulators; application of auxiliary layer incorporating third insulator and first metal; formation of temporary rectangular components with vertical side walls in auxiliary layer; and also formation of gate electrode (gate), drain/source areas, and conducting contact layer to source-gate-drain. Gate electrode is formed by sequential deposition of fourth insulator on vertical-wall rectangular components of auxiliary layer and second insulator of substrate, plasma chemical etching of fourth insulator to form first half of first spacer on vertical wall of rectangular component, deposition and plasma chemical etching of gate electrode material to form first half of first spacer of gate, deposition and plasma chemical etching of fifth insulator to form second half of first spacer on gate; in the process first metal of auxiliary layer and second insulator of gate insulator are used as shielding masks of underlayers during plasma chemical etching; after that spacer-gate-spacer layers formed in the process are used as mask for next doping of drain/source contact areas thereby ensuring offset of doping area relative to gate channel. Then second bilateral spacer is formed on side walls of gate and used for deep doping and also for organizing conducting areas of metal silicide at silicon contact points from deposited layer of second metal, whereupon second metal remaining on two spacers after siliconizing is removed thereby forming self-aligned source-gate-drain conducting contact areas.

EFFECT: reduced length of gate electrode, enlarged range of manufacturing capabilities.

9 cl, 11 dwg