METHOD OF MANUFACTURING A HIGH-SPEED SILICON MOS TRANSISTOR Russian patent published in 2024 - IPC H01L21/335 H01L29/68 

FIELD: microelectronics.

SUBSTANCE: invention relates to microelectronics, namely to making semiconductor transistors with reduced channel length. Method of manufacturing a high-speed silicon MOS transistor includes the formation of areas of drain, source, gate, gate dielectric, at that, according to the invention, the gate is made T-shaped with near-wall areas of silicon oxide, for this purpose transistor pocket is created on silicon structure by silicon layer doping and etching along mask, then a layer of silicon oxide is deposited and by means of etching along a mask corresponding to the design standard of the transistor, forming a through hole to the previous layer, then by depositing silicon oxide and subsequent etching, forming the wall regions, after which gate dielectric is created on doped silicon layer, then forming the transistor gate by depositing a layer of polycrystalline silicon and subsequent chemical-mechanical polishing, then, silicon oxide is removed by etching and heavily doped silicon regions are formed – the source and drain of the transistor by implantation of an impurity and subsequent annealing, then depositing silicon oxide with thickness exceeding the height of the formed gate layer, it is planarised by polishing to a layer of polycrystalline silicon and the formation of the gate is completed by depositing a layer of polycrystalline silicon and etching it and silicon oxide on the gate mask.

EFFECT: invention provides faster operation of the MOS transistor due to reduced channel length and wider field of application.

1 cl, 11 dwg, 1 tbl