METHOD FOR MANUFACTURING A LATERAL DMOS TRANSISTOR WITH AN INCREASED BREAKDOWN VOLTAGE Russian patent published in 2023 - IPC H01L29/68 

FIELD: microelectronics.

SUBSTANCE: semiconductor silicon transistors with an increased value of the breakdown voltage “source-drain” and a small occupied area on the chip. In the proposed method for manufacturing a lateral DMOS transistor, a well of the required height is created on a bulk silicon wafer by etching silicon on a mask, a pocket and a drift region of the transistor are formed. Then, by the method of deposition of silicon oxide and further planarization of the surface, the formed well is filled. Next, a gate dielectric is formed by high-temperature oxidation, and the transistor gate is formed by deposition of a polysilicon layer and its further etching on the mask. Then, the source-drain regions are formed by the method for impurity ion implantation and further high-temperature annealing. Next, transistor spacers are formed by deposition and further reactive ion etching of silicon oxide.

EFFECT: expansion of the scope of manufactured ICs based on such transistors, a high degree of integration of transistors on a chip.

1 cl, 8 dwg