BIPOLAR TRANSISTOR MANUFACTURING PROCESS Russian patent published in 2005 - IPC

FIELD: microelectronics; building integrated circuits around bipolar transistors produced using self-combined technologies.

SUBSTANCE: proposed process for manufacturing bipolar transistors includes covering of silicon substrate with first silicon oxide layer and first polycrystalline silicon layer, doping of first polycrystalline silicon layer with base impurity, settling-down of silicon nitride layer, opening of windows in silicon nitride, first polycrystalline silicon, and silicon oxide layers until silicon is exposed, etching of first silicon oxide layer under first polycrystalline silicon layer, settling-down of second polycrystalline silicon layer, heat treatment and formation of second silicon oxide layer by oxidizing second polycrystalline silicon layer until silicon is exposed, opening of windows in second silicon oxide layer, settling-down of third polycrystalline silicon layer, its doping with transistor emitter impurity, and heat treatment. Prior to doping first polycrystalline silicon layer, third silicon oxide layer is formed on the latter, windows are opened in silicon nitride layers, in third silicon oxide layer, and in first polycrystalline silicon layer using plasmachemical etching method until first silicon oxide layer is exposed. This is followed by etching first silicon oxide layer under polycrystalline silicon layer by liquid etching method. Prior to opening windows in second silicon oxide layer second silicon nitride layer is settled down and etched by plasmachemical method until second silicon oxide layer is exposed. Second silicon oxide layer is removed by liquid etching method, and silicon surface is doped with transistor active base impurity before settling down third polycrystalline silicon layer. Proposed process is characterized in reduction of number of plasmachemical silicon etching processes in transistor emitter window thereby ensuring reliable insulation between polycrystalline silicon layers functioning as transistor electrodes, as well as in separate doping of active base and emitter.

EFFECT: improved structural perfection of silicon layer and reproducibility of transistor physical structure parameters.

3 cl, 16 dwg