PATTERNED IC PRODUCTION METHOD Russian patent published in 2008 - IPC H05K3/00 

FIELD: electrical engineering.

SUBSTANCE: invention is designed to be used in IC production techniques and can be used for manufacture of patterned IC for electronic hardware. The proposed method includes forming the circuitry components on dielectric substrate by metallisation of mechanically pre-made components, application of copper layers and the lead-tin alloy on the entire blank surface, application of the additional screening paint layer resistant to etching solutions, mechanical grinding the protective paint and lead-tin layer coats off to the copper outer layer, withdrawal of the base metal outside the patterned outline and IR flowing of the lead-tin alloy and repair of finished ICs in case they lose moisture resistance. The dielectric substrate metallisation is effected step-be-step, i.e. first, chemically, by copper layer till minimum thickness of, at least, 3 to 5 microns with subsequent galvanic build-up of the said layer up to 25 to 50 microns. Second, the blank is coated with the 9 to 12-micron-thick lead-tin alloy layer over its entire surface and, thereafter, the paint screening layer is applied only all along the mechanical pattern outline. Now, the excess screening layer is removed till the copper surface layer. The copper layer outside the pattern outline and removal of the screening layer are effected prior to flowing of the lead-tin alloy layer. Finally, the finished patterned IC are impregnated with an organic complex compound.

EFFECT: application of ICs at high temperature along with lower etching rejects and higher moisture resistance.

9 dwg, 1 ex, 1 tbl