FUNCTIONAL STRUCTURE FOR PARALLEL ADDER WITH PRE-ENTERED CARRY BITS (VERSIONS) Russian patent published in 2010 - IPC G06F7/50

Abstract RU 2381545 C2

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices and carrying out arithmetic operations of summing intermediate products in a multiplier. In the first version each bit of the device contains two logic inverters, three NAND elements and three NOR elements.

EFFECT: faster operation.

2 cl, 9 dwg, 4 ex

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RU 2 381 545 C2

Authors

Petrenko Lev Petrovich

Dates

2010-02-10—Published

2008-04-29—Filed