METHOD OF PARALLEL BOOLEAN SUMMATION OF USER ANALOGUE SIGNALS OF COMPONENTS EQUIVALENT TO BINARY NUMBER SYSTEM Russian patent published in 2010 - IPC G06F7/50 

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out arithmetic operations in position-sign codes. The method involves the following: from input analogue signals n_i and m_i in the i^th bit, analogue signals of the first intermediate logical sum S¹ _i through logical functions OR1 and a second intermediate logic sum S² _i through logical functions AND1; a positive derived analogue signal +S³ _i is formed through logical function AND2 from a pre-modified function NOT1 on the level of the analogue signal S ¹ _i and the first intermediate sum S¹ _i-1 of the (i-1)^th bit, and a conditionally negative derived analogue signal -S³ _i is formed through logical function AND3 from analogue signal S¹ _i and a pre-modified function NOT2 on the level of analogue signal S¹ _i-1 of the first intermediate sum S¹ _i-1 of the (i-1)^th bit; analogue signal +S³ _i is combined with analogue signal +S² _i through logical function OR2 and the level of the analogue signal of the resultant argument +S*_i is modified, which corresponds to the procedure of removing the active logical zero, which forms if the composite analogue signal +S*_i and the conditionally negative derived analogue signal -S³ _i simultaneously assume active analogue signal levels; the active analogue signal level is removed when the conditionally negative derived analogue signal -S³ _i coincides with the analogue signal of the second intermediate sum +S² _i.

EFFECT: faster operation.

5 dwg