METHOD TO PRODUCE LOCAL LOW-RESISTANCE AREAS OF TITANIUM SILICIDE IN INTEGRATED CIRCUITS Russian patent published in 2013 - IPC H01L21/8238 B82B3/00 

FIELD: electricity.

SUBSTANCE: invention relates to the technology of making integrated circuits on the basis of complementary transistors with the structure of metal - oxide - semiconductor (CMOS IC). The method to produce local low-resistance areas of titanium silicide in integrated circuits consists in generation of active and passive elements of CMOS IC on the basis of areas of n and p type of conductivity in a silicon substrate and a layer of polycrystalline silicon, deposition of a blocking layer, formation of a photoresistive mask, etching of the blocking layer, removal of the photoresistive mask, cleaning of the silicon surface, application of the titanium layer onto the surface of silicon and the blocking layer, annealing of the titanium layer in nitrogen, removal of titanium, which did not react with silicon, and additional annealing in nitrogen. The blocking layer is a film of titanium nitride with thickness of 5-20 nm, produced by means of physical spraying of a titanium target in nitrogen atmosphere, and the blocking layer is removed in process of removal of titanium, which did not react with silicon.

EFFECT: preservation of electrophysical and structural parameters of active and passive elements in integrated circuits on the basis of complementary transistors with a structure of metal - oxide - semiconductor when generating titanium silicide.

5 dwg, 1 tbl