METHOD FOR MANUFACTURING A MOS TRANSISTOR ON A SILICON-ON-INSULATOR STRUCTURE Russian patent published in 2022 - IPC H01L29/68 

FIELD: electronics.

SUBSTANCE: invention relates to the field of microelectronics, namely, to manufacturing semiconductor devices with a high value of breakdown voltage of the gate dielectric and a lower value of tunnelling current through said dielectric. A transistor well is created on an SOI plate; a silicon nitride region corresponding to the design standard of the transistor is formed. Low-alloyed source and drain region are then formed with a layer of silicon oxide thereon, the silicon nitride is removed. A silicon oxide layer is deposited, wall regions are formed by means of reactive ion etching. The gate silicon oxide is formed next, then the transistor gate is formed by depositing and mask etching polycrystalline silicon, followed by mask-free etching silicon oxide and forming the high-alloyed source and drain regions.

EFFECT: higher value of breakdown voltage of the gate dielectric of a submicron MOS transistor on the SOI structure, higher reliability of integrated circuits on such transistors.

1 cl, 9 dwg, 1 tbl