FIELD: electricity.
SUBSTANCE: method is purposed for use at incoming and final quality inspection of CMOS of digital integrated circuits and assessment of their temperature margin. A logical element of an integrated circuit (IC) selected as a heat source is heated up by passing heating current through p-n junction formed by a heavily doped p+ area connected electrically to IC output and n-substrate of p-channel MOS transistors electrically connected to IC power output in the first case or through p-n junction formed by a heavily doped p+ area connected electrically to IC output and p-well of n-channel MOS transistors electrically connected to the common IC power output in the second case. Voltage of heat-sensitive parameter is measured at p-n junction of another local element during passage of direct survey current and p-n junction is formed by a heavily doped p+ area connected electrically to IC output and p-well of n-channel MOS transistors connected electrically with common IC power output in the first case and a heavily doped p+ area connected electrically to IC output and n-substrate of p-channel MOS transistors connected to IC power output in the second case. IC power outputs are interconnected during measurement. Measurement of electrical heating power is determined as production of heating current passing through p-n junction by voltage drop in it. Heat-transfer resistance is determined as ratio of change in voltage of a heat-sensitive element to change in electrical heating power and known voltage temperature coefficient of a heat-sensitive element.
EFFECT: reduced measurement error.
4 dwg
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Authors
Dates
2013-08-20—Published
2011-10-28—Filed