FIELD: information technology.
SUBSTANCE: array substrate (20) includes TFT elements and pixel electrodes, respectively connected to the TFT elements which are arranged in form of an array on an insulating substrate. The array substrate includes: gate bus lines made from a first metal material (M1); source bus lines made from a second metal material (M2); pixel electrodes made from a third metal material (M3); a clock wiring (72) made from the first metal material (M1); a branch wiring (74) made from the second metal material (M2); and a connection conductor (102) made from the third metal material (M3), the connection conductor (102) connecting the clock wiring (72) and the branch wiring (74) at a connection part (80) in a peripheral area (24), the connection part (80) having a branch wiring through-hole (112), which exposes the branch wiring (74) which is covered with the connection conductor (102), and overlaps the clock wiring (72) at least partly in a plan view.
EFFECT: improved image quality.
40 cl, 17 dwg
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Authors
Dates
2013-08-27—Published
2009-11-05—Filed