FIELD: electrical engineering.
SUBSTANCE: invention relates to multilevel semiconductor devices. Semiconductor node comprises a first crystal unit and a second chip unit. First crystal unit includes a first crystal having an upper surface of the first crystal and a bottom surface of the first crystal and a first edge extending transversely from the first crystal, the first edge including an upper surface of the first edge located near the upper surface of the first crystal and a bottom surface of the first edge disposed near the bottom surface of the first crystal, the lower surface of the first crystal and the bottom surface of the first edge are located near the input and output arrays for the semiconductor node. Second crystal unit includes a second crystal having an upper surface of the second crystal and a bottom surface of the second crystal and a second edge extending laterally from the second crystal, the second edge including an upper surface of the second edge located near the upper surface of the second crystal and a bottom surface of the second edge located near the bottom surface of the second crystal. In addition, the semiconductor assembly includes a plurality of conductive tracks extending outwardly beyond the second crystal toward the bottom surface of the second edge. At least the upper surface of the first edge is the uppermost surface of the first block of the crystal, and the lower surface of the second edge is the lowest surface of the second block of the crystal. In this case, a plurality of conductive tracks are disposed between the upper surface of the first crystal and the lower surface of the second crystal. Semiconductor node also comprises one or more transition holes extending through at least one of the first and second edges, wherein said one or more transition holes are connected to the first and second crystals by a plurality of conductive paths and at least one of the first and second edges.
EFFECT: multilevel semiconductor device is proposed.
23 cl, 11 dwg
