METHOD FOR THREE-DIMENSIONAL MULTI-CHIP PACKAGING OF INTEGRATED MEMORY MICROCIRCUITS Russian patent published in 2019 - IPC H01L21/48 

FIELD: electrical engineering.

SUBSTANCE: invention relates to the field of the integrated memory microcaps and is intended to reduce the warping of the manufactured microcircuits with arrangement of several NAND-memory chips in the single BGA-type housing. Method includes all stages of packaging from provision of silicon plates to cutting of substrates with sealed micro assemblies into separate integral microcircuits of memory.

EFFECT: reduced warping is achieved due to selection of substrate and compound materials having optimum values of temperature expansion coefficients, minimum difference between these coefficients, as well as use of minimum difference between substrate temperatures during crystal mounting and compound pouring; additional reduction of warping is ensured by finding optimum thickness of mounted silicon crystals, at which thickness of stack of silicon crystals is approximately equal to thickness of integrated microcircuit of memory less double of thickness of substrate.

1 cl, 4 dwg