FIELD: microelectronic engineering.
SUBSTANCE: claimed is a method for reducing thermal stresses during processing of semiconductor wafers with a height-developed topography, consisting in placing a semiconductor wafer with a side whereon a height-developed topography is made in form of protruding parts separated by recesses on a carrier wafer and attaching said wafer to the carrier wafer by means of an adhesive layer with a thickness of 1 to 10 mcm. To increase the contact area of the semiconductor wafer with the carrier wafer, additional elements of a material corresponding to the material of the semiconductor wafer are therein placed in the recess areas, constituting protruding parts with flat end platforms located in a common plane passing through the end platforms of the protruding parts of the topography. The total surface area of the flat end platforms of the protruding parts of the additional elements of no less than 1 mm2 is therein provided.
EFFECT: reduced thermal stresses in a semiconductor (silicon) wafer with a height-developed topography during technological processing thereof.
4 cl, 9 dwg
